This invention relates to an oversampling clock recovery circuit.
The development in an electronic industry is striking and alternation of generations in electronic applied machine instruments is increasing at a high rate. Therefore, smooth alternation of generations always is a problem in common.
In basic network communications as well, transmission rate in digital data has been shifting from 622 megahertz (MHz) to 1.25 gigahertz (GHz) and further to 2.5 GHz. Accordingly, request has been made in development of clock recovery circuits which can make a clock signal sufficiently follow high-speed input data. In prior art, in order to cope with high-speed in such a date transmission, an oversampling type clock recovery circuit has been proposed. The oversampling type clock recovery circuit samples successive several bits of data using a number of clock signals each having a low frequency compared with data rate and phase compares using a plurality of phase-comparators. The oversampling is a method of carrying out sampling by making two or more clock edges correspond to one bit of an input data. A method of carrying out sampling by making n clock edges correspond to one bit of the input data is called an n-times oversampling. An 8-times oversampling is disclosed in Japanese Unexamined Patent Publication Tokkai No. Hei 9-233061 or JP-A 9-233061. A 2-times oversampling is disclosed in U.S. Pat. No. 5,633,899 issued to Alan Fiedler et al.
However, when the oversampling clock recovery circuit designed for use in data communications for a data rate of 2.5 Gbps receives data having a data rate of 1.25 Gbps or 622 Mbps, it is disadvantageous in that an error rate increases, in the manner which will later be in detail described in conjunction with FIGS. 4A through 4G.